1. Field
The exemplary embodiments relate to a semiconductor memory device and a method of operating the same.
2. Description of the Related Art
Synchronous semiconductor memory devices operate in synchronization with an external system clock to improve operating speeds.
Among the synchronous semiconductor memory devices, a synchronous DRAM (SDRAM) may input/output one piece of data during one cycle of a clock in synchronization with a rising edge of the clock. By contrast, a double data rate SDRAM (DDR SDRAM) is configured to input/output data in synchronization not only with a rising edge of the clock but also a falling edge of the clock. Therefore, the DDR SDRAM may continuously input/output two pieces of data during one cycle of a clock. That is to say, the DDR SDRAM can implement an operating speed of greater than two times without increasing the frequency of the clock, compared to a conventional SDRAM.
During a read operation, the semiconductor memory device may output to an external device a data strobe signal (DQS) that is a kind of an echo clock signal with data. The reason of the foregoing is to allow the semiconductor memory device to notify a CPU or a controller of accurate timings of output data and to minimize a time skew generated between chips in a memory chipset. The data strobe signal DQS is basically maintained at a high state of impedance (Hi-Z) and makes a transition to a low clock when at one clock prior to the data being output. Accordingly, an external device is notified that data is to be output, prior to the output, thereby allowing the external device to accurately receive the data. Thereafter, the data strobe signal DQS is repeatedly toggled between a high level and a low level, and data is output while the data strobe signal DQS is toggled. The data strobe signal DQS is then maintained at a low level during half a clock during which the last data is output in order to notify the external device that the output of data is completed, and goes back to the Hi-Z state.
A period in which the data strobe signal DQS is maintained at a low level for one clock period prior to data being output is referred to as a preamble, and a period in which the data strobe signal DQS is maintained at a low level for half a clock period prior to the last data being output is referred to as a postamble. That is to say, the data strobe signal DQS notifies an external device of a data output timing start and a data output timing end using the preamble and the postamble. The external device determines a precise timing for receiving data using the preamble of the data strobe signal DQS applied earlier than the data.